1. Field
An embodiment of the present invention relates to a delay analysis device, a delay analysis method, and a delay analysis program.
2. Description of the Related Art
There has been known a method in which a timing analysis is utilized when the delay of an integrated circuit is analyzed.
The timing analysis is an analysis method in which the operating frequency of a chip is evaluated in a design stage using a CAD (Computer Aided Design) tool and it is confirmed whether or not a target operating frequency is realized. For example, when the chip is designed with the goal of realizing an operating frequency of 2.5 GHz, it is analyzed whether or not signals are transmitted among all memory devices in a time less than or equal to 400 ps, that is the inverse of 2.5 GHz.
Typically, the timing analysis is classified as either a static timing analysis or a dynamic timing analysis. In addition, the static timing analysis is classified into two analysis methods, namely, a static timing analysis (hereinafter, referred to as STA) which has been usually used, and a statistical static timing analysis (hereinafter, referred to as SSTA) which is an analysis method that has been proposed in recent years.
As examples of the STA, there are a deterministic static timing analysis, a path-based STA, and a block-based STA. In addition, as examples of the SSTA, there are a path-based SSTA and a block-based SSTA.
Here, the STA, the SSTA, and the block-based SSTA will be described with reference to FIG. 8.
In the STA, when the delay of a path is calculated, the delay values of individual elements such as gate devices and wires included in the path are subjected to a cumulative calculation performed in a direction toward the latter stages. The delay values at this time are individual fixed numerical values. The path-based STA is a method in which the cumulative calculation is performed preferentially in the direction of the depth of a circuit, and the block-based STA is a method in which the cumulative calculation is performed preferentially in the direction of the width of the circuit.
In the example illustrated in FIG. 8, in the case of the path-based STA, the cumulative calculation is performed for a path leading from a latch A to a latch C, a path leading from a latch B to the latch C, a path leading from the latch B to a latch D, in this order. In the case of the block-based STA, the delay values of individual gates are simultaneously accumulated in units of gates in directions from both the latch A and the latch B to an output side. Since a gate p has two inputs, a cumulative processing operation for the gate p is performed at the time when the cumulative calculation for both a path leading from the latch A to the gate p and a path leading from the latch B to the gate p is completed. When a processing operation for calculating a maximum delay is performed, the delay of the gate p is accumulated in the greater one of the two accumulated delays of the two paths leading to the gate p and the processing operation proceeds forward. In such a case in which one gate has a plurality of inputs, an operation in which a maximum delay is selected is called “MAX operation”.
In contrast to the STA described above, in the SSTA, the delay values of individual elements such as gate devices and wires included in a path are not expressed as individual fixed numerical values but as probability density functions in which horizontal axis correspond to delay values and vertical axis correspond to probability densities. In addition, regarding the accumulation of the delay of the path, while a simple numerical value is added in the STA, the statistical addition of a probability density function is performed in the SSTA. In addition, while the MAX operation is a numerical operation in which a large numerical value is left in the STA, a statistics operation called “statistical MAX of two probability density functions” is performed in the SSTA. In the processing operation performed in the SSTA, the block-based SSTA is a method in which a cumulative calculation is performed preferentially in the direction of the width of the circuit, in the same way as described in the explanation of the block-based STA.    [Patent Document 1] Japanese Laid-open patent publication 2008-102837    [Patent Document 2] Japanese Laid-open patent publication 8-6988    [Patent Document 3] Japanese Laid-open patent publication 2000-222452    [Patent Document 4] Japanese Laid-open patent publication 2001-67383    [Non-patent Document 1] Jing-Jia Liou et al., “False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation”, International Conference on Computer Aided Design, 2002, pp 566-569    [Non-patent Document 2] Shuji Tsukiyama et al., “Techniques to Remove False Paths in Statistical Static Timing Analysis”, ASICON, 2001, pp 39-44    [Non-patent Document 3] Rajesh Garg et al., “On the Improvement of Statistical Timing Analysis”, ICCD, 2006    [Non-patent Document 4] Vikram Iyengar et al., “Variation-Aware Performance Verification Using At-Speed Structural Test And Statistical Timing”, International Conference on Computer Aided Design, 2007, pp 405-412